Most computers and other digital systems have a system memory which often consists of dynamic random access memory (“DRAM”) devices. DRAM devices are fairly inexpensive because a DRAM memory cell needs relatively few components to store a data bit as compared with other types of memory cells. Thus, a large system memory can be implemented using DRAM devices for a relatively low cost.
Commonly, DRAM devices are arranged on memory modules, such as single in-line memory modules (“SIMMs”) and dual in-line memory modules (“DIMMs”). A representative module is shown in FIG. 1. The module 100 features a number of DRAM devices 104 mounted on an insulative substrate 108 through which the DRAM devices 104 are operably coupled through communications lines 110 such as conductive traces or other similar signal carrying devices to a memory hub 112. The module 100 interfaces with a system (not shown) through a series of conductive terminals 116 or other means through which control, data, and address information is communicated between the system and the module 100. A typical memory module 100 may support a number of DRAM devices 104 which supports an array of single-bit storage devices. A number of these DRAM devices 104 are arrayed in a parallel fashion such that, upon the module 100 receiving a specified address, the memory hub 112 will cause a data bit stored at the same address in each of the array of memory devices 104 to be retrieved to effectively retrieve a full data word. For example, if the memory module 100 features eight DRAM devices 104, each address applied to the module 100, the memory hub 112 will cause an eight-bit byte to be retrieved from the DRAM devices 104.
The proliferation of this modular design has a number of advantages, ranging from the ability to provide a large memory capacity in a relatively small package to greatly simplifying the installation process as compared to the painstaking process of installing individual memory chips. Beyond these more obvious advantages of modular design, however, is the additional functionality which is made possible by the use of the memory hub 112 (FIG. 1). To name one example, the memory hub 112 can include one or more registers, allowing address, data, and/or control information to be latched. The latching of this information allows for synchronous operations using this information without concern for data transiency problems such as race, skew, or synchronization problems which might result if the module had to be perfectly in synchronization with the system bus in receiving and outputting data. In addition, computer systems employing this architecture can have a higher bandwidth because a processor can access one memory device while another memory device is responding to a prior memory access. For example, the processor can output write data to one of the memory devices in the system while another memory device in the system is preparing to provide read data to the processor. Continually, new techniques are being developed to exploit the control permitted by the presence of the memory hub 112 central control logic on these memory modules 100.
Returning to the DRAM devices themselves, while DRAM devices do provide a relatively inexpensive way to provide a large system memory, DRAM devices suffer from the disadvantage that their memory cells must be continually refreshed. Refreshing memory cells consumes an appreciable quantity of power. Because of this drain of power, an important topic in DRAM design is how to reduce the power consumed in refreshing DRAM cells.
Once such technique for reducing power consumption is the implementation of a self-refresh cycle. FIG. 2 depicts a block diagram of a conventional DRAM device 200 enabled to use self-refresh. The DRAM device 200 is accessed through the address lines 210, the data lines 212, and a number of control lines 220-232. These control lines include CKE (clock enable) 220, CK* (clock signal—low) 222, CK (clock signal) 224, CS* (chip select—low enable) 226, WE* (write select—low enable) 228, CAS* (column address strobe—low enable) 230, and RAS* (row address strobe—low enable) 230. The address lines 210, data lines 212, and control lines 220-232, enable the system to read and write data to the actual memory banks 250, as well as control the refreshing of the DRAM device 200. The control logic 260 controls the read, write, and refresh operations of the DRAM device 200. The control logic 260 directs the operations of the DRAM device 200 as a function of the signals received at the control lines 220-232.
A DRAM device 200 typically is refreshed using an auto-refresh cycle, which is triggered by the system and operates synchronously with the system clock. More specifically, with the CKE 220 and WE* 228 control lines driven high, and the CS* 226, RAS* 230 and CAS* 232 control lines driven low, the rising edge of the next clock signal initiates an auto-refresh of the next row of the memory banks 250. Once the system initiates an auto-refresh cycle, the refresh counter 270 is incremented by one, and the row of the memory banks 250 corresponding to the updated count stored in the refresh counter 270 is refreshed. The refresh counter 270 maintains its count to track what row is next to be refreshed when the next auto-refresh cycle is initiated. This process repeats continuously. In a typical DRAM, having 4,096 rows and a maximum refresh interval of 64 milliseconds in its operational mode, a command to refresh one row would have to be issued approximately every 15 to 16 microseconds.
Although the auto-refresh process is a relatively simple one, auto-refresh requires that hundreds or thousands of times per second, thousands of control logic and access transistors within the devices depicted in FIG. 2 and described in the foregoing description must be energized to refresh the array, consuming power. In addition, resistance of the conductors through the memory array to address each and every transistor in each and every row consumes even more power. Still more power is consumed by transistors used in the sense amplifiers which read and refresh the memory cells in respective columns. Moreover, power is needed to actually charge each of the thousands of capacitors storing data bits in the array.
Implementation of a self-refresh cycle saves some of the power consumed as compared with auto-refresh. Initiation of a self-refresh cycle places a DRAM device 200 in a continual, indefinite refresh cycle to preserve the data stored in the DRAM device 200. A self-refresh command typically is issued during a period when useful read and write requests will not be forthcoming, for example, when a user has placed the computing system into a sleep or standby mode. A self-refresh command is triggered by driving the CS* 226, RAS* 230 and the CAS* 232 control lines low, driving the WE* 228 control line high, and, this time, driving the CKE 220 control line low. This command causes the self-refresh control logic 280 to periodically and repeatedly refresh every one of its rows, and also places all data, address, and control lines into a “don't care” state, with the exception of the CKE 220 control line. Driving the CKE 220 control line high ends the self-refresh state, removing the other control lines out of the “don't care” state.
During a self-refresh cycle, with most of the control lines in a don't care state, devices in the DRAM device 200 will not be switching to decode memory addresses and perform read or write commands, thus current and voltage fluctuations in the DRAM device 200 are reduced. This relatively stable condition tends to ameliorate electrical and thermal effects which contribute to current leakage from the capacitors of the memory cells. As a result, while the memory cells still need to be refreshed to preserve the integrity of the data stored therein, the memory cells do not need to be refreshed as frequently as during an operational state. During self-refresh, the contents of the memory cells can be preserved by refreshing a row less frequently than required during normal operation. In self-refresh state, for example, the rows might not need to be refreshed for a period up to twice as long, or perhaps slightly longer, than is permitted during an operational state.
While self-refresh can save an appreciable amount of power, self-refresh traditionally is implemented on a system-wide basis, often along with other power-saving techniques: For example, when a computer is placed in a standby mode, virtually every device in the computer enters a standby mode, i.e., the display is shut down, the hard disk is stopped, the memory is placed in a self-refresh state, and other systems are similarly put to “sleep.”
Operating systems, such as Windows 2000® do allow for more advanced power management options, and a user can select an interval of disuse after which the hard disk, the display, and the entire system will power down. In addition, some operating systems or utilities provide for additional power management choices allowing a user to choose operating parameters ranging between maximum performance at one extreme and maximum power savings at another extreme, or some intermediate compromise choice to suit the user's preferences. Still, while all these options save power, the only means to avoid wasting power in system memory remains an all or nothing, standby or not proposition.
What is needed is a way to save power which might be wasted in system memory. It is to this end that the present invention is directed.